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1dfbd4eff2
-Add new preset dimensions to the right click menu of the width and height fields in the editor. -Change QSS stylesheets to properly handle tabs. -Make tabs rectangular by default. For some reason, they had always been triangular. --Bug fixes -Incremental rendering times in the editor were wrong. --Code changes -Migrate to Qt6. There is probably more work to be done here. -Migrate to VS2022. -Migrate to Wix 4 installer. -Change installer to install to program files for all users. -Fix many VS2022 code analysis warnings. -No longer use byte typedef, because std::byte is now a type. Revert all back to unsigned char. -Upgrade OpenCL headers to version 3.0 and keep locally now rather than trying to look for system files. -No longer link to Nvidia or AMD specific OpenCL libraries. Use the generic installer located at OCL_ROOT too. -Add the ability to change OpenCL grid dimensions. This was attempted for investigating possible performance improvments, but made no difference. This has not been verified on Linux or Mac yet.
441 lines
10 KiB
C
441 lines
10 KiB
C
/*******************************************************************************
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* Copyright (c) 2019-2020 The Khronos Group Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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******************************************************************************/
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/**
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* This is a header-only utility library that provides OpenCL host code with
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* routines for converting to/from cl_half values.
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*
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* Example usage:
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*
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* #include <CL/cl_half.h>
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* ...
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* cl_half h = cl_half_from_float(0.5f, CL_HALF_RTE);
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* cl_float f = cl_half_to_float(h);
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*/
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#ifndef OPENCL_CL_HALF_H
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#define OPENCL_CL_HALF_H
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#include <CL/cl_platform.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Rounding mode used when converting to cl_half.
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*/
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typedef enum
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{
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CL_HALF_RTE, // round to nearest even
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CL_HALF_RTZ, // round towards zero
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CL_HALF_RTP, // round towards positive infinity
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CL_HALF_RTN, // round towards negative infinity
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} cl_half_rounding_mode;
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/* Private utility macros. */
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#define CL_HALF_EXP_MASK 0x7C00
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#define CL_HALF_MAX_FINITE_MAG 0x7BFF
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/*
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* Utility to deal with values that overflow when converting to half precision.
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*/
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static inline cl_half cl_half_handle_overflow(cl_half_rounding_mode rounding_mode,
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uint16_t sign)
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{
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if (rounding_mode == CL_HALF_RTZ)
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{
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// Round overflow towards zero -> largest finite number (preserving sign)
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return (sign << 15) | CL_HALF_MAX_FINITE_MAG;
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}
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else if (rounding_mode == CL_HALF_RTP && sign)
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{
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// Round negative overflow towards positive infinity -> most negative finite number
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return (1 << 15) | CL_HALF_MAX_FINITE_MAG;
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}
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else if (rounding_mode == CL_HALF_RTN && !sign)
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{
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// Round positive overflow towards negative infinity -> largest finite number
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return CL_HALF_MAX_FINITE_MAG;
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}
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// Overflow to infinity
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return (sign << 15) | CL_HALF_EXP_MASK;
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}
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/*
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* Utility to deal with values that underflow when converting to half precision.
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*/
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static inline cl_half cl_half_handle_underflow(cl_half_rounding_mode rounding_mode,
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uint16_t sign)
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{
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if (rounding_mode == CL_HALF_RTP && !sign)
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{
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// Round underflow towards positive infinity -> smallest positive value
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return (sign << 15) | 1;
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}
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else if (rounding_mode == CL_HALF_RTN && sign)
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{
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// Round underflow towards negative infinity -> largest negative value
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return (sign << 15) | 1;
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}
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// Flush to zero
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return (sign << 15);
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}
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/**
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* Convert a cl_float to a cl_half.
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*/
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static inline cl_half cl_half_from_float(cl_float f, cl_half_rounding_mode rounding_mode)
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{
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// Type-punning to get direct access to underlying bits
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union
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{
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cl_float f;
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uint32_t i;
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} f32;
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f32.f = f;
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// Extract sign bit
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uint16_t sign = f32.i >> 31;
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// Extract FP32 exponent and mantissa
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uint32_t f_exp = (f32.i >> (CL_FLT_MANT_DIG - 1)) & 0xFF;
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uint32_t f_mant = f32.i & ((1 << (CL_FLT_MANT_DIG - 1)) - 1);
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// Remove FP32 exponent bias
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int32_t exp = f_exp - CL_FLT_MAX_EXP + 1;
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// Add FP16 exponent bias
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uint16_t h_exp = (uint16_t)(exp + CL_HALF_MAX_EXP - 1);
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// Position of the bit that will become the FP16 mantissa LSB
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uint32_t lsb_pos = CL_FLT_MANT_DIG - CL_HALF_MANT_DIG;
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// Check for NaN / infinity
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if (f_exp == 0xFF)
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{
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if (f_mant)
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{
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// NaN -> propagate mantissa and silence it
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uint16_t h_mant = (uint16_t)(f_mant >> lsb_pos);
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h_mant |= 0x200;
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return (sign << 15) | CL_HALF_EXP_MASK | h_mant;
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}
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else
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{
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// Infinity -> zero mantissa
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return (sign << 15) | CL_HALF_EXP_MASK;
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}
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}
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// Check for zero
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if (!f_exp && !f_mant)
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{
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return (sign << 15);
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}
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// Check for overflow
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if (exp >= CL_HALF_MAX_EXP)
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{
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return cl_half_handle_overflow(rounding_mode, sign);
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}
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// Check for underflow
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if (exp < (CL_HALF_MIN_EXP - CL_HALF_MANT_DIG - 1))
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{
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return cl_half_handle_underflow(rounding_mode, sign);
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}
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// Check for value that will become denormal
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if (exp < -14)
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{
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// Denormal -> include the implicit 1 from the FP32 mantissa
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h_exp = 0;
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f_mant |= 1 << (CL_FLT_MANT_DIG - 1);
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// Mantissa shift amount depends on exponent
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lsb_pos = -exp + (CL_FLT_MANT_DIG - 25);
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}
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// Generate FP16 mantissa by shifting FP32 mantissa
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uint16_t h_mant = (uint16_t)(f_mant >> lsb_pos);
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// Check whether we need to round
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uint32_t halfway = 1 << (lsb_pos - 1);
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uint32_t mask = (halfway << 1) - 1;
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switch (rounding_mode)
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{
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case CL_HALF_RTE:
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if ((f_mant & mask) > halfway)
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{
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// More than halfway -> round up
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h_mant += 1;
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}
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else if ((f_mant & mask) == halfway)
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{
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// Exactly halfway -> round to nearest even
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if (h_mant & 0x1)
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h_mant += 1;
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}
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break;
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case CL_HALF_RTZ:
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// Mantissa has already been truncated -> do nothing
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break;
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case CL_HALF_RTP:
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if ((f_mant & mask) && !sign)
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{
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// Round positive numbers up
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h_mant += 1;
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}
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break;
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case CL_HALF_RTN:
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if ((f_mant & mask) && sign)
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{
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// Round negative numbers down
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h_mant += 1;
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}
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break;
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}
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// Check for mantissa overflow
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if (h_mant & 0x400)
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{
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h_exp += 1;
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h_mant = 0;
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}
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return (sign << 15) | (h_exp << 10) | h_mant;
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}
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/**
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* Convert a cl_double to a cl_half.
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*/
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static inline cl_half cl_half_from_double(cl_double d, cl_half_rounding_mode rounding_mode)
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{
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// Type-punning to get direct access to underlying bits
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union
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{
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cl_double d;
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uint64_t i;
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} f64;
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f64.d = d;
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// Extract sign bit
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uint16_t sign = f64.i >> 63;
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// Extract FP64 exponent and mantissa
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uint64_t d_exp = (f64.i >> (CL_DBL_MANT_DIG - 1)) & 0x7FF;
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uint64_t d_mant = f64.i & (((uint64_t)1 << (CL_DBL_MANT_DIG - 1)) - 1);
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// Remove FP64 exponent bias
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int64_t exp = d_exp - CL_DBL_MAX_EXP + 1;
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// Add FP16 exponent bias
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uint16_t h_exp = (uint16_t)(exp + CL_HALF_MAX_EXP - 1);
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// Position of the bit that will become the FP16 mantissa LSB
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uint32_t lsb_pos = CL_DBL_MANT_DIG - CL_HALF_MANT_DIG;
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// Check for NaN / infinity
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if (d_exp == 0x7FF)
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{
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if (d_mant)
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{
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// NaN -> propagate mantissa and silence it
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uint16_t h_mant = (uint16_t)(d_mant >> lsb_pos);
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h_mant |= 0x200;
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return (sign << 15) | CL_HALF_EXP_MASK | h_mant;
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}
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else
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{
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// Infinity -> zero mantissa
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return (sign << 15) | CL_HALF_EXP_MASK;
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}
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}
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// Check for zero
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if (!d_exp && !d_mant)
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{
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return (sign << 15);
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}
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// Check for overflow
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if (exp >= CL_HALF_MAX_EXP)
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{
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return cl_half_handle_overflow(rounding_mode, sign);
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}
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// Check for underflow
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if (exp < (CL_HALF_MIN_EXP - CL_HALF_MANT_DIG - 1))
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{
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return cl_half_handle_underflow(rounding_mode, sign);
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}
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// Check for value that will become denormal
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if (exp < -14)
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{
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// Include the implicit 1 from the FP64 mantissa
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h_exp = 0;
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d_mant |= (uint64_t)1 << (CL_DBL_MANT_DIG - 1);
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// Mantissa shift amount depends on exponent
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lsb_pos = (uint32_t)(-exp + (CL_DBL_MANT_DIG - 25));
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}
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// Generate FP16 mantissa by shifting FP64 mantissa
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uint16_t h_mant = (uint16_t)(d_mant >> lsb_pos);
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// Check whether we need to round
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uint64_t halfway = (uint64_t)1 << (lsb_pos - 1);
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uint64_t mask = (halfway << 1) - 1;
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switch (rounding_mode)
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{
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case CL_HALF_RTE:
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if ((d_mant & mask) > halfway)
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{
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// More than halfway -> round up
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h_mant += 1;
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}
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else if ((d_mant & mask) == halfway)
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{
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// Exactly halfway -> round to nearest even
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if (h_mant & 0x1)
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h_mant += 1;
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}
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break;
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case CL_HALF_RTZ:
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// Mantissa has already been truncated -> do nothing
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break;
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case CL_HALF_RTP:
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if ((d_mant & mask) && !sign)
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{
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// Round positive numbers up
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h_mant += 1;
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}
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break;
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case CL_HALF_RTN:
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if ((d_mant & mask) && sign)
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{
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// Round negative numbers down
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h_mant += 1;
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}
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break;
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}
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// Check for mantissa overflow
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if (h_mant & 0x400)
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{
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h_exp += 1;
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h_mant = 0;
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}
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return (sign << 15) | (h_exp << 10) | h_mant;
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}
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/**
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* Convert a cl_half to a cl_float.
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*/
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static inline cl_float cl_half_to_float(cl_half h)
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{
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// Type-punning to get direct access to underlying bits
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union
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{
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cl_float f;
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uint32_t i;
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} f32;
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// Extract sign bit
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uint16_t sign = h >> 15;
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// Extract FP16 exponent and mantissa
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uint16_t h_exp = (h >> (CL_HALF_MANT_DIG - 1)) & 0x1F;
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uint16_t h_mant = h & 0x3FF;
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// Remove FP16 exponent bias
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int32_t exp = h_exp - CL_HALF_MAX_EXP + 1;
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// Add FP32 exponent bias
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uint32_t f_exp = exp + CL_FLT_MAX_EXP - 1;
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// Check for NaN / infinity
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if (h_exp == 0x1F)
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{
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if (h_mant)
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{
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// NaN -> propagate mantissa and silence it
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uint32_t f_mant = h_mant << (CL_FLT_MANT_DIG - CL_HALF_MANT_DIG);
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f_mant |= 0x400000;
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f32.i = (sign << 31) | 0x7F800000 | f_mant;
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return f32.f;
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}
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else
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{
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// Infinity -> zero mantissa
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f32.i = (sign << 31) | 0x7F800000;
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return f32.f;
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}
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}
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// Check for zero / denormal
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if (h_exp == 0)
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{
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if (h_mant == 0)
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{
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// Zero -> zero exponent
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f_exp = 0;
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}
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else
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{
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// Denormal -> normalize it
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// - Shift mantissa to make most-significant 1 implicit
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// - Adjust exponent accordingly
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uint32_t shift = 0;
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while ((h_mant & 0x400) == 0)
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{
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h_mant <<= 1;
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shift++;
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}
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h_mant &= 0x3FF;
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f_exp -= shift - 1;
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}
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}
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f32.i = (sign << 31) | (f_exp << 23) | (h_mant << 13);
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return f32.f;
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}
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#undef CL_HALF_EXP_MASK
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#undef CL_HALF_MAX_FINITE_MAG
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#ifdef __cplusplus
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}
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#endif
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#endif /* OPENCL_CL_HALF_H */
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